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Si4455
5.3. Interrupts
The Si4455 is capable of generating an interrupt signal when certain events occur. The chip notifies the
microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal
will be generated when any one (or more) of the interrupt events occur. The nIRQ pin will remain low until the
microcontroller reads the Interrupt Status Registers. The nIRQ output signal will then be reset until the next change
in status is detected.
The interrupt sources are grouped into three categories: packet handler, chip status, and modem. The individual
interrupts in these groups can be enabled/disabled in the interrupt property registers, 0x0101, 0x0102, and 0x0103.
An interrupt must be enabled for it to trigger an event on the nIRQ pin. The interrupt group must be enabled as well
as the individual interrupts in API property 0x0100.
When an interrupt event occurs and the nIRQ pin is low, the interrupts are read and cleared using the
GET_INT_STATUS command. By default all interrupts will be cleared once read. The instantaneous status of a
specific function may be read if the specific interrupt is enabled or disabled. The status results are provided after
the interrupts and can be read with the same commands as the interrupts. The status bits will give the current state
of the function whether the interrupt is enabled or not. The following is a list of possible interrupts:
?? Chip
status
?? Modem
status
?? Packet handler status
?? Packet sent
?? Packet received
?? CRC error
?? Invalid preamble detected
?? Invalid sync detected
?? Preamble detected
?? Sync detected
?? State change
?? Command error
?? Chip ready
?? TX FIFO almost empty
?? RX FIFO almost full
?? RSSI interrupt
Rev 1.1
29
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